Why double patterning is needed below the single-exposure pitch limit, how LELE and SADP work, what coloring, odd-cycle conflicts and stitches mean, and how DPT changes placement, routing, extraction and DRC, with illustrative examples, a debug flowchart and interview Q&As.
What max transition, max capacitance and max fanout DRVs check, where the limits come from (Liberty and SDC), how tools prioritize them, worked examples, fixes such as sizing, repeaters, buffer trees and cloning, plus a debug flowchart and interview Q&As.
What electromigration is, Black's equation and the Blech effect, average vs RMS vs peak current limits, worked examples for clock and power nets, where EM is handled in the physical design flow, and how to debug and fix EM violations.
Why cell delay can fall as temperature rises at low supply voltage, how mobility and threshold voltage compete, and what temperature inversion means for STA corners, hold sign-off, DVFS modes and timing fixes.
Latch-up in CMOS explained for physical designers: the parasitic PNPN (SCR) mechanism, triggers, holding voltage and current, tap cells and guard rings, SOI/FinFET, JEDEC JESD78 testing, layout checks and interview questions.
What PODE and CPODE are, how single and double diffusion breaks differ, and what cell-edge rules mean for placement, legalization, fillers and ECOs at FinFET and GAA nodes.
How multi-bit flip-flops save clock power, which flops can be banked, the timing and useful-skew trade-offs, and a practical method for debanking, with worked examples.
What via pillars and via ladders are, why they matter at advanced nodes, when to insert EM-required and performance pillars, their costs, and how to verify the benefit.
Backside power delivery moves the power grid below the transistors. What it changes in floorplanning, PDN, placement, CTS, routing, IR/EM and thermal signoff, with a practical checklist.
Learn clock gating in VLSI: dynamic power savings, why AND-gate gating glitches, how the integrated clock gating (ICG) cell works, clock gating checks with examples and interview questions.