Routing congestion in VLSI explained for physical design engineers: how global routers measure GCell capacity, demand and overflow, cell density vs pin density, global, local and layer congestion, floorplan, logic and placement causes, fixes with halos, partial blockages and cell padding, the timing impact, a debugging flowchart and interview Q&As.
Scan chain reordering in VLSI physical design explained: why synthesis scan order wastes wirelength, what the scan DEF (START/STOP, FLOATING, ORDERED, PARTITION, MAXBITS) allows, clock-domain, edge-order and lockup-latch rules, chain balancing, scan shift hold timing, verification and ATPG regeneration, with illustrative examples, a debugging flowchart and interview Q&As.
What PODE and CPODE are, how single and double diffusion breaks differ, and what cell-edge rules mean for placement, legalization, fillers and ECOs at FinFET and GAA nodes.
How multi-bit flip-flops save clock power, which flops can be banked, the timing and useful-skew trade-offs, and a practical method for debanking, with worked examples.
Understanding the Performance (Timing) Before going to understand the performance (timing), lets understand how timing is getting checked. At placement stage we have the placement of cells information, but we don’t have connection information in between the cells so how…
What is Placement Optimization? Depending on the stages of the design, optimization can include the following operations: Secondary PG Routing As we know there are many partitions now a days, so we are dealing with UPF and number of power…
Refine Placement (Legalization) There are number of tool options which we can use for refining the placement, like you can set some micron distance so that tool will not move those cells more than specified distance. Detailed Placement
During placement, following three stages happens: Global Placement Global placement is very first stage of the placement where cells are placed inside the core area for the first time looking at the timing and congestion. Global Placement aims at generating…
Pre-Placement Sanity Checks Before proceeding with the placement of standard cells, pre-placement sanity checks are performed to ensure the design is in good shape. These checks help identify potential issues early, preventing delays in the later stages of physical design.…
What is Placement? Once we are done with the floorplan after placing all the physical cells inside the core boundary, we are left with standard cells which are still sitting out of the core design area. Now we need to…