Multi-Bit Flip-Flops (MBFF): Banking, Debanking and Timing Trade-offs
How multi-bit flip-flops save clock power, which flops can be banked, the timing and useful-skew trade-offs, and a practical method for debanking, with worked examples.
Category CTS
Clock Gating and Integrated Clock Gating (ICG) in VLSI: Complete Guide
Learn clock gating in VLSI: dynamic power savings, why AND-gate gating glitches, how the integrated clock gating (ICG) cell works, clock gating checks with examples and interview questions.
Clock Tree Synthesis (CTS)
What is a Clock? A clock signal is like the heartbeat of a digital system. It pulses at regular intervals, switching between high and low states with steady rise and fall transitions. In an ideal case, the clock has a…
Signal Integrity and Crosstalk
What is Signal Integrity and Crosstalk? Let’s take one example. I am doing work from home in my study room attending meeting and my family is sitting in the TV room and watching some news. Even though I am sitting…
Integrated Clock Gating (ICG) Cell & Related Concepts
Integrated Clock Gating (ICG) Cell & Related Concepts We always have target to close the design by meeting the PPA (Power, Performance, Area). Clock consumes most of the power as it has high switching activities. Being specific, clock consumes almost…
Duty Cycle & Pulse Width
Why clock duty cycle distorts through the clock tree, how STA computes minimum pulse width slack (worked example), how to read the report, and a step-by-step fix method, with interview questions.
Useful Skew
Useful skew is very important concept in CTS. Let’s discuss this through an example. In the above picture, we can see that the first path is having positive 15 ps of skew, second path is having negative 5 ps of…
CTS Spec File
CTS Spec File CTS spec file contains the below information: 1. Inverters or buffers to be defined which will be used to balance the clock tree. 2. CTS Exceptions (End points of clock tree). 3. Skew group information. 4. Contains…