The CMOS inverter explained for VLSI and physical design engineers: PMOS/NMOS structure and switch model, VTC regions, switching threshold, noise margins, propagation delay and slew, dynamic, short-circuit and leakage power, standard-cell layout and latch-up, its role in CTS and STA, a timing debug flowchart and interview Q&As.
Routing congestion in VLSI explained for physical design engineers: how global routers measure GCell capacity, demand and overflow, cell density vs pin density, global, local and layer congestion, floorplan, logic and placement causes, fixes with halos, partial blockages and cell padding, the timing impact, a debugging flowchart and interview Q&As.
Scan chain reordering in VLSI physical design explained: why synthesis scan order wastes wirelength, what the scan DEF (START/STOP, FLOATING, ORDERED, PARTITION, MAXBITS) allows, clock-domain, edge-order and lockup-latch rules, chain balancing, scan shift hold timing, verification and ATPG regeneration, with illustrative examples, a debugging flowchart and interview Q&As.
ECO (Engineering Change Order) in VLSI physical design explained: timing, DRV, noise, leakage and functional ECOs, pre-mask vs post-mask (metal-only) changes, spare cells, the sign-off STA to place-and-route ECO loop, what to re-verify after every ECO and how to debug an ECO that will not converge, with illustrative examples and interview Q&As.
Multicycle paths and false paths in STA explained for physical design and timing engineers: how set_multicycle_path moves setup and hold checks, why setup N needs hold N-1, -start vs -end across clocks, valid and dangerous false paths, clock groups, exception precedence and a debugging flow, with illustrative examples and interview Q&As.
The difference between a latch and a flip-flop explained for physical design and STA engineers: level vs edge triggering, master-slave structure, where setup and hold are checked, time borrowing, phase-dependent hold, ICG and lockup latches, and unintended RTL latches, with illustrative examples, a debug flowchart and interview Q&As.
IR drop analysis in VLSI explained for physical design engineers: where supply and ground drop come from, static vs dynamic IR drop, vectorless and vector-based analysis, how IR drop affects setup and hold, and how to debug and fix hotspots, with illustrative examples, a flowchart and interview Q&As.
How crosstalk works in VLSI physical design: coupling capacitance between aggressor and victim nets, rise/fall glitches and overshoot/undershoot, delta delay and its effect on setup and hold, timing windows in SI-aware STA, and practical fixes, with illustrative examples, a debugging flowchart and interview Q&As.
How time budgeting splits the timing of paths that cross block boundaries in a hierarchical design: input and output delays in block SDC, ways to divide slack, clocks, exceptions and hold budgets, and how to debug and re-budget interface violations, with illustrative examples, a flowchart and interview Q&As.
What technology DRCs check and why: width, width- and run-length-dependent spacing, end-of-line, minimum area, enclosure, cut, notch and density rules, how the tech LEF differs from the sign-off runset, and how to debug DRC violations, with illustrative examples, a flowchart and interview Q&As.