Double Patterning (DPT) in VLSI: LELE, SADP, Coloring and Stitches for Physical Design
Design Rule Violations (DRVs) in VLSI: Max Transition, Max Capacitance and Max Fanout
Electromigration (EM) in VLSI: Black’s Equation, Limits and Fixes
Temperature Inversion in VLSI: Causes, STA Corners and Fixes
Latch-up in CMOS: Parasitic SCR, Triggers, Prevention and JESD78 Testing
PODE vs CPODE: Diffusion Breaks, Cell Edges and Placement
Multi-Bit Flip-Flops (MBFF): Banking, Debanking and Timing Trade-offs
Via Pillars (Via Ladders) in Physical Design: Timing and EM Guide
Backside Power Delivery (BSPDN): How It Changes the Physical Design Flow
