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iVLSI Technoglogies
  • Synthesis
    • Synthesis Overview and Inputs
    • Types of Synthesis
    • Physical Synthesis
    • RTL Quality Effect on Synthesis
  • Physical Design
    • Physical Design Flow
    • Physical Design Inputs
      • Physical Design Inputs
      • Synthesized Netlist
      • Design Exchange Format (DEF)
      • Physical Library (LEF)
      • Timing Library (.lib)
      • Standard Design Constraints (.sdc)
      • Unified Power Format (.upf)
    • Floorplan
      • Floorplan Overview
      • Macros
      • Macro Placement Guidelines
      • Floorplan Module Constraints
      • Blockages
      • Decap Cells
      • AON Cells
      • TIE Cells in VLSI
      • Isolation Cells
      • Retention Flops
      • Level Shifter Cells
      • Boundary Cap Cells/End Caps
      • Tap Cells
      • Power Switch Cells
      • PG Grid Insertion
      • Pin & Power Mux Placement
    • Placement
      • Placement Overview
      • Pre Placement Sanity Checks
      • Global Placement
      • Refine & Detailed Placement
      • Scan Chain Reordering
      • Placement Optimization
      • Congestion
      • Performance (Timing)
      • Power
    • Clock Tree Synthesis (CTS)
      • CTS Overview
      • CTS Spec File
      • Useful Skew
      • Duty Cycle & Pulse Width
      • ICG Cell & Related Concepts
      • Signal Integrity & Crosstalk
    • Routing
      • Routing Overview
      • Metal Layers
      • Pitch, Spacing & Offset
      • VIAs
  • Scripting
    • SHELL Scripting
      • Basic Linux Commands
      • GREP Commands
      • AWK Commands
      • SED Commands
      • GVIM Commands
    • TCL Scripting
      • Basics of TCL
      • Decision in TCL
      • LOOPS in TCL
      • ARRAY in TCL
      • String in TCL
      • List in TCL
      • Procedure in TCL
      • File IO in TCL
      • Regular Expressions in TCL
      • Practical Exposure to writing TCL with examples
    • PERL Scripting
  • Interview QA
    • Floorplan Q n A
    • Placement Q n A
    • CTS Q n A
    • Routing Q n A
  • Jobs
  • Forum
  • News
iVLSI Technoglogies

Clock Gating and Integrated Clock Gating (ICG) in VLSI: Complete Guide

Clock Gating and Integrated Clock Gating (ICG) - iVLSI featured image
  • October 13, 2026

Time Borrowing (Cycle Stealing) in VLSI: Latch Timing with Examples

Time Borrowing (Cycle Stealing) in VLSI - iVLSI featured image
  • October 13, 2026

Static Timing Analysis (STA) in VLSI: Setup, Hold, OCV/AOCV/POCV, CRPR

Static Timing Analysis (STA) in VLSI - iVLSI featured image
  • October 13, 2026

Clock Tree Synthesis (CTS)

  • September 27, 2025
  • 7 Comments

Physical Synthesis

  • March 8, 2025
  • 1 Comment

Recovery and Removal Time Analysis: The Secret to Avoiding Circuit Failures

  • March 8, 2025

Chipmaker Intel begins informing customers of price hike plans for a wide range of products

chipmaker-intel-begins-informing-customers-of-price-hike-plans-for-a-wide- range-of-products
  • July 22, 2022

STMicroelectronics and GlobalFoundries aim to advance FD-SOI ecosystem with new 300mm manufacturing facility in France

stmicroelectronics-and-globalfoundries-aim-to-advance-FD-SOI-ecosystem-with-new-300mm-manufacturing-facility-in-france
  • July 20, 2022

Robert Bosch wants to spend $3 billion to strengthen European chip supply

robert-bosch-wants-to-spend-$3-billion-to-strengthen-european-chip-supply
  • July 19, 2022
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