Physical-Only Cells in VLSI: Tap, Endcap, Filler and Decap
OCV, AOCV and POCV in STA: Derates, CRPR and Sign-off
Recovery and Removal in STA: Async Reset Timing Checks
Useful Skew in VLSI: CTS, Setup/Hold Trade-offs
Combinational vs Sequential Circuits: Timing, STA and PD
CMOS Inverter: Working, VTC, Noise Margins, Delay and Power
Routing Congestion in VLSI: Causes, Analysis and Fixes
Scan Chain Reordering in VLSI: Scan DEF, Partitions, Hold Timing and ATPG Impact
ECO in VLSI Physical Design: Timing ECOs, Functional ECOs, Spare Cells and Metal-Only Fixes
