Scan Chain Reordering in VLSI: Scan DEF, Partitions, Hold Timing and ATPG Impact
ECO in VLSI Physical Design: Timing ECOs, Functional ECOs, Spare Cells and Metal-Only Fixes
Multicycle Path and False Path in STA: Setup/Hold Multipliers, -start/-end and Exception Precedence
Difference Between Latch and Flip-Flop: Structure, Timing Checks and STA
IR Drop Analysis in VLSI: Static vs Dynamic IR Drop, Timing Impact and Fixes
Crosstalk in VLSI: Glitch Noise, Delta Delay, Timing Windows and Fixes
Time Budgeting in VLSI: Block-Level Constraints for Hierarchical Timing Closure
Technology DRCs in VLSI: Width, Spacing, End-of-Line, Min Area, Enclosure and Density Rules
Double Patterning (DPT) in VLSI: LELE, SADP, Coloring and Stitches for Physical Design
