VIAs in VLSI
What are VIAs in VLSI? Types of VIAs Single Cut Via Single cut via is a type of via where we have only one poly connection between the two connecting metal layers. Below picture will explain better. Multi Cut Via…
Category Physical Design
Pitch, Spacing & Offset
Pitch The distance between the center to center of the metal is called as pitch. In the below picture, B is pitch. Spacing Spacing is the distance between the edge to edge metal layers. The distance A is spacing in…
Metal Layers
What are Metal Layers? In the above figure, we can see that two points need to get connected through the different metal layers which is horizontal and vertical.
Routing
Overview of Routing Types of Routes Clock physical routing is completed during CTS after clock buffer insertion. Pre-Route Checks The pre-route checks that need to be done are as follows: Goals of Routing
Signal Integrity and Crosstalk
What is Signal Integrity and Crosstalk? Let’s take one example. I am doing work from home in my study room attending meeting and my family is sitting in the TV room and watching some news. Even though I am sitting…
Integrated Clock Gating (ICG) Cell & Related Concepts
Integrated Clock Gating (ICG) Cell & Related Concepts We always have target to close the design by meeting the PPA (Power, Performance, Area). Clock consumes most of the power as it has high switching activities. Being specific, clock consumes almost…
Duty Cycle & Pulse Width
Duty Cycle The basic definition of duty cycle is on_time/(on_time+ Off_time). The on time and off time totally depends upon the rise transition and fall transition. Due to transition differences, duty cycle changes and hence the calculation becomes bad. Practically,…
Useful Skew
Useful skew is very important concept in CTS. Let’s discuss this through an example. In the above picture, we can see that the first path is having positive 15 ps of skew, second path is having negative 5 ps of…
CTS Spec File
CTS Spec File CTS spec file contains the below information: 1. Inverters or buffers to be defined which will be used to balance the clock tree. 2. CTS Exceptions (End points of clock tree). 3. Skew group information. 4. Contains…
Clock Tree Synthesis (CTS)
Clock Tree Synthesis Clock – A signal with constant rise and fall with ideally equal width (50% rise and 50% fall of the signal width) helps to control data propagation through the clock elements like Flip-Flop, Latches etc. The clock…