Integrated Clock Gating (ICG) Cell & Related Concepts We always have target to close the design by meeting the PPA (Power, Performance, Area). Clock consumes most of the power as it has high switching activities. Being specific, clock consumes almost…
Duty Cycle The basic definition of duty cycle is on_time/(on_time+ Off_time). The on time and off time totally depends upon the rise transition and fall transition. Due to transition differences, duty cycle changes and hence the calculation becomes bad. Practically,…
Useful skew is very important concept in CTS. Let’s discuss this through an example. In the above picture, we can see that the first path is having positive 15 ps of skew, second path is having negative 5 ps of…
CTS Spec File CTS spec file contains the below information: 1. Inverters or buffers to be defined which will be used to balance the clock tree. 2. CTS Exceptions (End points of clock tree). 3. Skew group information. 4. Contains…
What is a Clock? A clock is a periodic signal with constant rise and fall transitions, ideally having a 50% duty cycle (equal rise and fall time). It plays a crucial role in controlling data propagation through clock elements such…
Power We will discuss more about power analysis in ECO section while working on PDN, for now let’s take basic glimpse of the power analysis and consumption. There are basically 2 types of power consumption in VLSI design: 1. Dynamic…
Understanding the Performance (Timing) Before going to understand the performance (timing), lets understand how timing is getting checked. At placement stage we have the placement of cells information, but we don’t have connection information in between the cells so how…
What is Congestion? If the number of required routing resources exceeds the available routing tracks, the area becomes congested. High congestion leads to detours and poorer results. Severe congestion can make the design non-routable, meaning routing will not converge if…
What is Placement Optimization? Depending on the stages of the design, optimization can include the following operations: Secondary PG Routing As we know there are many partitions now a days, so we are dealing with UPF and number of power…
We understand how scan chains are inserted and their impact on the circuit. Now, let’s focus on the main topic: how the tool optimizes the scan chain. Scan chain reordering helps optimize routing resources and reduces congestion in the design.…