Routing in VLSI Physical Design

We need the Clock Tree Synthesis database before going to the Route stage in physical design, where we have placed all the cells present in the design.
Route creates physical connections to all the logical connections present in the design with the help of metal layers. These connections can be clock or data.

There are basically three routes:
- PG Route
  
  Power/Ground physical routing is completed during floorplan. Secondary PG routing happens just after STD cell placement.
- Clock Route

Clock physical routing is completed during CTS after clock buffer insertion.

- Signal Route
  
  All the signal routing are completed after all the cells are placed which is called as routing stage.
Routing and its optimization are done after taking care of QORs and physical DRCs. Once these counts are reasonable, we go for the ECO stage.

The pre-route checks that need to be done are as follows:

All the Physical cells and Standard cells should be placed properly inside the core area.
Clock cells should be placed and clock routing should be completed. Clock NDR should be applied for the required or all clock nets.
Acceptable congestion, Timing (Setup/Hold), Power and Logical DRCs.
We should fix all the assign statements where 1’b0 should be connected via TIE low and similarly 1’b1 should be connected to TIE high cell.
ATPG and scan coverage should be proper. The entire design should have testability.
PDN report (Low Power report) should be clean.
Logical Equivalence should be clean.
Max Tran, Max Cap, Max Load etc. violations should not be too high. Marginal can be handled during routing or ECO stage.

Routing