Physical Synthesis

When it comes to digital design, Physical Synthesis plays a crucial role in optimizing timing, congestion, and power. It acts as the bridge between logic-level design and circuit-level implementation, ensuring that designs transition smoothly into physical form while maintaining performance.

To start Physical Synthesis, we need essential inputs such as:

• RTL (Register Transfer Level) code
• SDC (Synopsys Design Constraints)
• Timing libraries
• Physical libraries
• UPF (Unified Power Format)
• DEF (Design Exchange Format)
• Other technology files

At this stage, the design undergoes initial placement and trial routing, converting the logic-level design into a circuit-level representation. This early-stage optimization significantly improves congestion, timing, and power while reducing unnecessary iterations in later design stages.

How Physical Synthesis Works

Physical Synthesis performs coarse placement with a focus on congestion-aware and timing-aware optimizations. Alongside placement, it executes a trial route that enhances RC (resistance-capacitance) correlation with physical design tools. The result? Better performance with fewer redesign cycles.

Steps in Synthesis

Synthesis is carried out in three main stages:

1. Architecture-Level or High-Level Synthesis
2. Logic-Level GTECH Optimization
3. Gate-Level or Mapping Optimization

Let’s break down each step in detail.

1. Read Inputs

This is the foundation of the synthesis process. All design inputs, including RTL, timing constraints, and physical libraries, are loaded into the tool.

2. Elaborate

At this stage, the RTL consists only of Boolean expressions. The synthesis tool performs hierarchical analysis, breaking down the logic into building blocks and mapping them to GTECH cells—technology-independent standard cells used for early optimization.

During elaboration, the tool checks for:

• Unique hierarchies in the design
• Unresolved references (which, if found, must be debugged in the RTL)
• Timing loops that could lead to design failures

Here’s what happens in this phase:

1. Configure timing and physical libraries.
2. Define scenarios for timing and leakage analysis.
3. Read and analyze RTL code.
4. Link logic groups with the internal tool-built libraries.
5. Uniquify the design by renaming duplicate cells to avoid conflicts.
6. Detect and resolve timing loops.

Once elaboration is complete, the log file is analyzed to fix errors and warnings such as missing files, linking issues, or timing violations.

3. Compile

Now that the design is elaborated, it’s time for cell mapping. The tool replaces technology-independent GTECH cells with actual cells from the standard cell library, considering:

• SDC constraints
• User settings (e.g., “Don’t use cell list”)
• Register removal (due to constant propagation)

During this step, Integrated Clock Gating (ICG) is also applied, optimizing power consumption by gating unused clock signals.

4. Optimization

Optimization ensures that the synthesized design meets timing, power, and area constraints by performing:

• Logic restructuring to minimize delays
• Buffer insertion for better signal integrity
• Clock tree synthesis for optimized clock distribution

5. Design for Test (DFT)

At this stage, scan chains and testability structures are inserted to enable manufacturing tests.

6. Quality Checks

The synthesized design undergoes a series of validation checks, including:

• Timing analysis (setup, hold, recovery, and removal checks)
• Power estimation
• Congestion analysis
• Functional equivalence verification

7. Outputs

Once all synthesis steps are complete, the following files are generated:

• Netlist (Verilog or VHDL)
• Standard Delay Format (SDF) for timing analysis
• Reports for timing, area, and power

Final Thoughts

Physical Synthesis is a game-changer in modern chip design. By integrating early-stage optimizations, it ensures that the design is efficient, congestion-free, and meets timing requirements before moving to later physical design stages.

Skipping this step can lead to unnecessary iterations, missed timing goals, and wasted design cycles. But when done right? You’ll get a high-performance, power-efficient chip that’s ready for real-world use. 🚀