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  • Synthesis
    • Synthesis Overview and Inputs
    • Types of Synthesis
    • Physical Synthesis
    • RTL Quality Effect on Synthesis
  • Physical Design
    • Physical Design Flow
    • Physical Design Inputs
      • Physical Design Inputs
      • Synthesized Netlist
      • Design Exchange Format (DEF)
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      • Timing Library (.lib)
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      • Floorplan Overview
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      • Decap Cells
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      • TIE Cells in VLSI
      • Isolation Cells
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      • Pin & Power Mux Placement
    • Placement
      • Placement Overview
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      • Refine & Detailed Placement
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      • Placement Optimization
      • Congestion
      • Performance (Timing)
      • Power
    • Clock Tree Synthesis (CTS)
      • CTS Overview
      • CTS Spec File
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    • SHELL Scripting
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      • Basics of TCL
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      • String in TCL
      • List in TCL
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      • File IO in TCL
      • Regular Expressions in TCL
      • Practical Exposure to writing TCL with examples
    • PERL Scripting
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iVLSI Technoglogies
  • Synthesis
    • Synthesis Overview and Inputs
    • Types of Synthesis
    • Physical Synthesis
    • RTL Quality Effect on Synthesis
  • Physical Design
    • Physical Design Flow
    • Physical Design Inputs
      • Physical Design Inputs
      • Synthesized Netlist
      • Design Exchange Format (DEF)
      • Physical Library (LEF)
      • Timing Library (.lib)
      • Standard Design Constraints (.sdc)
      • Unified Power Format (.upf)
    • Floorplan
      • Floorplan Overview
      • Macros
      • Macro Placement Guidelines
      • Floorplan Module Constraints
      • Blockages
      • Decap Cells
      • AON Cells
      • TIE Cells in VLSI
      • Isolation Cells
      • Retention Flops
      • Level Shifter Cells
      • Boundary Cap Cells/End Caps
      • Tap Cells
      • Power Switch Cells
      • PG Grid Insertion
      • Pin & Power Mux Placement
    • Placement
      • Placement Overview
      • Pre Placement Sanity Checks
      • Global Placement
      • Refine & Detailed Placement
      • Scan Chain Reordering
      • Placement Optimization
      • Congestion
      • Performance (Timing)
      • Power
    • Clock Tree Synthesis (CTS)
      • CTS Overview
      • CTS Spec File
      • Useful Skew
      • Duty Cycle & Pulse Width
      • ICG Cell & Related Concepts
      • Signal Integrity & Crosstalk
    • Routing
      • Routing Overview
      • Metal Layers
      • Pitch, Spacing & Offset
      • VIAs
  • Scripting
    • SHELL Scripting
      • Basic Linux Commands
      • GREP Commands
      • AWK Commands
      • SED Commands
      • GVIM Commands
    • TCL Scripting
      • Basics of TCL
      • Decision in TCL
      • LOOPS in TCL
      • ARRAY in TCL
      • String in TCL
      • List in TCL
      • Procedure in TCL
      • File IO in TCL
      • Regular Expressions in TCL
      • Practical Exposure to writing TCL with examples
    • PERL Scripting
  • Interview QA
    • Floorplan Q n A
    • Placement Q n A
    • CTS Q n A
    • Routing Q n A
  • Jobs
  • Forum
  • News
iVLSI Technoglogies

Google team uses artificial intelligence to make next-generation chips faster than humans

google-ai-chips
  • June 17, 2021

IPO Arm, Qualcomm boss said, we will buy

qualcomm-arm-ipo
  • June 16, 2021

Indie Semiconductor continues to pull back after the merger of SPAC

indie-semiconductor-spac
  • June 14, 2021

Intel says it has bid $2 billion to acquire SiFive

intel-sifive-acquisition
  • June 10, 2021

RTL Quality Effect on Synthesis

  • May 22, 2021

TSMC beats IBM’s 2nm chip technology hype with 1nm proposition

tsmc-beats-ibms-2nm-chip-technology-hype-with-1nm-proposition
  • May 20, 2021

South Korea plans to spend US$450 billion on semiconductors

south-korea-plans-to-spend-us$450-billion-on-semiconductors
  • May 18, 2021

Types of Synthesis

  • May 18, 2021

Synthesis Overview and Inputs

  • May 16, 2021
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