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iVLSI Technoglogies
  • Synthesis
    • Synthesis Overview and Inputs
    • Types of Synthesis
    • Physical Synthesis
    • RTL Quality Effect on Synthesis
  • Physical Design
    • Physical Design Flow
    • Physical Design Inputs
      • Physical Design Inputs
      • Synthesized Netlist
      • Design Exchange Format (DEF)
      • Physical Library (LEF)
      • Timing Library (.lib)
      • Standard Design Constraints (.sdc)
      • Unified Power Format (.upf)
    • Floorplan
      • Floorplan Overview
      • Macros
      • Macro Placement Guidelines
      • Floorplan Module Constraints
      • Blockages
      • Decap Cells
      • AON Cells
      • TIE Cells in VLSI
      • Isolation Cells
      • Retention Flops
      • Level Shifter Cells
      • Boundary Cap Cells/End Caps
      • Tap Cells
      • Power Switch Cells
      • PG Grid Insertion
      • Pin & Power Mux Placement
    • Placement
      • Placement Overview
      • Pre Placement Sanity Checks
      • Global Placement
      • Refine & Detailed Placement
      • Scan Chain Reordering
      • Placement Optimization
      • Congestion
      • Performance (Timing)
      • Power
    • Clock Tree Synthesis (CTS)
      • CTS Overview
      • CTS Spec File
      • Useful Skew
      • Duty Cycle & Pulse Width
      • ICG Cell & Related Concepts
      • Signal Integrity & Crosstalk
    • Routing
      • Routing Overview
      • Metal Layers
      • Pitch, Spacing & Offset
      • VIAs
  • Scripting
    • SHELL Scripting
      • Basic Linux Commands
      • GREP Commands
      • AWK Commands
      • SED Commands
      • GVIM Commands
    • TCL Scripting
      • Basics of TCL
      • Decision in TCL
      • LOOPS in TCL
      • ARRAY in TCL
      • String in TCL
      • List in TCL
      • Procedure in TCL
      • File IO in TCL
      • Regular Expressions in TCL
      • Practical Exposure to writing TCL with examples
    • PERL Scripting
  • Interview QA
    • Floorplan Q n A
    • Placement Q n A
    • CTS Q n A
    • Routing Q n A
  • Jobs
  • Forum
  • News
iVLSI Technoglogies

Cadence expands cooperation with TSMC and Microsoft to accelerate the timing approval of Giga-level designs in the cloud

Cadence-expands-cooperation-with-TSMC-and-Microsoft
  • December 13, 2021

Qualcomm CEO said the chip shortage will ease next year

Qualcomm-CEO-said-the-chip-shortage-will-ease-next-year
  • December 11, 2021

Intel uses Mobileye proceeds to chip factory

Intel-uses-Mobileye-proceeds-to-chip-factory
  • December 9, 2021

After the “best” semiconductor earnings conference call, Marvell will be in the “same camp” with AMD and Nvidia

Marvell-will-be-in-the-same-camp-with-AMD-and-Nvidia
  • December 6, 2021

TSMC in dispute with Intel

TSMC-in-dispute-with-Intel
  • December 4, 2021

Samsung spends 17 billion U.S. dollars to select Texas as the site

samsung-chose-new-17-billion-fab-at-texas
  • November 30, 2021

MediaTek joins hands with TSMC to launch the world’s first 7nm 8K resolution digital TV system-on-chip

mediatek-tsmc-unveil-7nm-8k-digital-tv-soc
  • November 29, 2021

Qualcomm’s new RF filter technology optimizes 5G connections

Qualcomm's-new-RF-filter-technology-optimizes-5G-connections
  • October 28, 2021

Micron plans to invest a US$7 billion DRAM factory in Japan

Micron-plans-to-invest-a-US$7-billion-DRAM-factory-in-Japan
  • October 26, 2021
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