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iVLSI Technoglogies
  • Synthesis
    • Synthesis Overview and Inputs
    • Types of Synthesis
    • Physical Synthesis
    • RTL Quality Effect on Synthesis
  • Physical Design
    • Physical Design Flow
    • Physical Design Inputs
      • Physical Design Inputs
      • Synthesized Netlist
      • Design Exchange Format (DEF)
      • Physical Library (LEF)
      • Timing Library (.lib)
      • Standard Design Constraints (.sdc)
      • Unified Power Format (.upf)
    • Floorplan
      • Floorplan Overview
      • Macros
      • Macro Placement Guidelines
      • Floorplan Module Constraints
      • Blockages
      • Decap Cells
      • AON Cells
      • TIE Cells in VLSI
      • Isolation Cells
      • Retention Flops
      • Level Shifter Cells
      • Boundary Cap Cells/End Caps
      • Tap Cells
      • Power Switch Cells
      • PG Grid Insertion
      • Pin & Power Mux Placement
    • Placement
      • Placement Overview
      • Pre Placement Sanity Checks
      • Global Placement
      • Refine & Detailed Placement
      • Scan Chain Reordering
      • Placement Optimization
      • Congestion
      • Performance (Timing)
      • Power
    • Clock Tree Synthesis (CTS)
      • CTS Overview
      • CTS Spec File
      • Useful Skew
      • Duty Cycle & Pulse Width
      • ICG Cell & Related Concepts
      • Signal Integrity & Crosstalk
    • Routing
      • Routing Overview
      • Metal Layers
      • Pitch, Spacing & Offset
      • VIAs
  • Scripting
    • SHELL Scripting
      • Basic Linux Commands
      • GREP Commands
      • AWK Commands
      • SED Commands
      • GVIM Commands
    • TCL Scripting
      • Basics of TCL
      • Decision in TCL
      • LOOPS in TCL
      • ARRAY in TCL
      • String in TCL
      • List in TCL
      • Procedure in TCL
      • File IO in TCL
      • Regular Expressions in TCL
      • Practical Exposure to writing TCL with examples
    • PERL Scripting
  • Interview QA
    • Floorplan Q n A
    • Placement Q n A
    • CTS Q n A
    • Routing Q n A
  • Jobs
  • Forum
  • News
iVLSI Technoglogies

Intel invests $100 million in Ohio and National Semiconductor Education and Research Corporation

Intel-invests-$100-million-in-Ohio-and-National-Semiconductor-Education-and-Research-Corporation
  • March 18, 2022

TSMC Taiwan’s 3-nanometer factory to mass produce next year

TSMC-Taiwans-3-nanometer-factory-to-mass-produce-next-year-1
  • March 15, 2022

Samsung expects profit to rise 52% amid global chip shortage

Samsung-expects-its-profits-to-jump-by-52%-amid-global-chip-shortage
  • January 21, 2022

Qualcomm and Microsoft are collaborating on chips for future AR glasses

Qualcomm-and-Microsoft-are-collaborating-on-chips-for-future-AR-glasses
  • January 19, 2022

Due to a shortage of chips, Texas Instruments is worth $170 billion

Due-to-a-shortage-of-chips-Texas-Instruments-is-worth-$170-billion
  • January 6, 2022

Chip company AMD will purchase silicon wafers worth US$2.1B from GlobalFoundries

amd-to-purchase-semiconductors-from-globalfoundries
  • January 4, 2022

India and Taiwan are negotiating on domestic semiconductor manufacturing centers; trade and investment agreements are also discussed

India-and-Taiwan-are-negotiating-on-domestic-semiconductor-manufacturing-centers
  • December 18, 2021

Cabinet approves an incentive plan of Rs 76,000 crores to attract semiconductor manufacturers

Cabinet-approves-an-incentive-plan-of-Rs-76,000-crores-to-attract-semiconductor-manufacturers
  • December 17, 2021

Cadence expands cooperation with TSMC and Microsoft to accelerate the timing approval of Giga-level designs in the cloud

Cadence-expands-cooperation-with-TSMC-and-Microsoft
  • December 13, 2021
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