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iVLSI Technoglogies
  • Synthesis
    • Synthesis Overview and Inputs
    • Types of Synthesis
    • Physical Synthesis
    • RTL Quality Effect on Synthesis
  • Physical Design
    • Physical Design Flow
    • Physical Design Inputs
      • Physical Design Inputs
      • Synthesized Netlist
      • Design Exchange Format (DEF)
      • Physical Library (LEF)
      • Timing Library (.lib)
      • Standard Design Constraints (.sdc)
      • Unified Power Format (.upf)
    • Floorplan
      • Floorplan Overview
      • Macros
      • Macro Placement Guidelines
      • Floorplan Module Constraints
      • Blockages
      • Decap Cells
      • AON Cells
      • TIE Cells in VLSI
      • Isolation Cells
      • Retention Flops
      • Level Shifter Cells
      • Boundary Cap Cells/End Caps
      • Tap Cells
      • Power Switch Cells
      • PG Grid Insertion
      • Pin & Power Mux Placement
    • Placement
      • Placement Overview
      • Pre Placement Sanity Checks
      • Global Placement
      • Refine & Detailed Placement
      • Scan Chain Reordering
      • Placement Optimization
      • Congestion
      • Performance (Timing)
      • Power
    • Clock Tree Synthesis (CTS)
      • CTS Overview
      • CTS Spec File
      • Useful Skew
      • Duty Cycle & Pulse Width
      • ICG Cell & Related Concepts
      • Signal Integrity & Crosstalk
    • Routing
      • Routing Overview
      • Metal Layers
      • Pitch, Spacing & Offset
      • VIAs
  • Scripting
    • SHELL Scripting
      • Basic Linux Commands
      • GREP Commands
      • AWK Commands
      • SED Commands
      • GVIM Commands
    • TCL Scripting
      • Basics of TCL
      • Decision in TCL
      • LOOPS in TCL
      • ARRAY in TCL
      • String in TCL
      • List in TCL
      • Procedure in TCL
      • File IO in TCL
      • Regular Expressions in TCL
      • Practical Exposure to writing TCL with examples
    • PERL Scripting
  • Interview QA
    • Floorplan Q n A
    • Placement Q n A
    • CTS Q n A
    • Routing Q n A
  • Jobs
  • Forum
  • News
iVLSI Technoglogies

Intel and TSMC express interest in building chip factories in India

Intel-and-TSMC-express-interest-in-building-chip-factories-in-India
  • May 10, 2022

Intel partners hail new U.S. chip fabrication facility

Intel-partners-hail-new-US-chip-fabrication-facility
  • May 8, 2022

ISMC invests $3 billion in semiconductor manufacturing in Karnataka

ISMC-invests-$3-billion-in-semiconductor-manufacturing-in-karnataka
  • May 7, 2022

Are semiconductor company performance decoupled from the economy? TSMC’s results are positive, but we’ll get a clearer picture soon

Are-semiconductor-company-performance-decoupled-from-the-economy-TSMCs-results-are positive
  • April 27, 2022

Intel opens latest expansion in Hillsboro, reaffirms Oregon’s importance to its future

Intel-opens-latest-expansion-in-Hillsboro-reaffirms-Oregons-importance-to-its-future
  • April 23, 2022

TSMC says 2nm chips will go into production in 2025

TSMC-says-2nm-chips-will-go-into-production-in-2025
  • April 21, 2022

Intel CEO Pat Gelsinger meets PM Modi and discusses technology

Intel-CEO-Pat-Gelsinger-meets-PM-Modi-and-discusses-technology
  • April 8, 2022

Intel plans $88 billion chip manufacturing expansion in Europe

Intel-plans-$88-billion-chip-manufacturing-expansion-in-Europe
  • March 22, 2022

Scientists are developing a new technique to boost chip yields on semiconductor wafers

Scientist-are-developing-a-new-technique-to-boost-chip-yields-on-semiconductor-wafers
  • March 20, 2022
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