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  • Synthesis
    • Synthesis Overview and Inputs
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  • Physical Design
    • Physical Design Flow
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      • Physical Design Inputs
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    • Placement
      • Placement Overview
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      • CTS Overview
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iVLSI Technoglogies
  • Synthesis
    • Synthesis Overview and Inputs
    • Types of Synthesis
    • Physical Synthesis
    • RTL Quality Effect on Synthesis
  • Physical Design
    • Physical Design Flow
    • Physical Design Inputs
      • Physical Design Inputs
      • Synthesized Netlist
      • Design Exchange Format (DEF)
      • Physical Library (LEF)
      • Timing Library (.lib)
      • Standard Design Constraints (.sdc)
      • Unified Power Format (.upf)
    • Floorplan
      • Floorplan Overview
      • Macros
      • Macro Placement Guidelines
      • Floorplan Module Constraints
      • Blockages
      • Decap Cells
      • AON Cells
      • TIE Cells in VLSI
      • Isolation Cells
      • Retention Flops
      • Level Shifter Cells
      • Boundary Cap Cells/End Caps
      • Tap Cells
      • Power Switch Cells
      • PG Grid Insertion
      • Pin & Power Mux Placement
    • Placement
      • Placement Overview
      • Pre Placement Sanity Checks
      • Global Placement
      • Refine & Detailed Placement
      • Scan Chain Reordering
      • Placement Optimization
      • Congestion
      • Performance (Timing)
      • Power
    • Clock Tree Synthesis (CTS)
      • CTS Overview
      • CTS Spec File
      • Useful Skew
      • Duty Cycle & Pulse Width
      • ICG Cell & Related Concepts
      • Signal Integrity & Crosstalk
    • Routing
      • Routing Overview
      • Metal Layers
      • Pitch, Spacing & Offset
      • VIAs
  • Scripting
    • SHELL Scripting
      • Basic Linux Commands
      • GREP Commands
      • AWK Commands
      • SED Commands
      • GVIM Commands
    • TCL Scripting
      • Basics of TCL
      • Decision in TCL
      • LOOPS in TCL
      • ARRAY in TCL
      • String in TCL
      • List in TCL
      • Procedure in TCL
      • File IO in TCL
      • Regular Expressions in TCL
      • Practical Exposure to writing TCL with examples
    • PERL Scripting
  • Interview QA
    • Floorplan Q n A
    • Placement Q n A
    • CTS Q n A
    • Routing Q n A
  • Jobs
  • Forum
  • News
iVLSI Technoglogies

Global Placement

  • August 19, 2020
  • 2 Comments

Pre Placement Sanity Checks

  • August 18, 2020

Placement

  • August 17, 2020
  • 4 Comments

Pin Placement & Power Mux Placement

  • August 16, 2020

Power Ground Grid Insertion

  • August 15, 2020

Power Switch Cell Placement in VLSI

  • August 14, 2020

Tap Cell Placement in VLSI

  • August 13, 2020

Boundary Cap Cells/End Cap Placement

  • August 12, 2020

Level Shifter Cell

  • August 11, 2020
  • 2 Comments
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