Isolation Cell Placement
Isolation cell placement Type of Isolation Cells Verify DRC We verify DRC after the Isolation cell placement to look for PG rail connectivity, Geometry checks, Metal short, etc. We must fix these DRCs before going…
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TIE Cells in VLSI
What are TIE Cells? Types of TIE Cells There are two types of TIE Cells: – Tie High One pin to VDD and other to signal nets – Tie Low One pin to VSS and other to…
AON Cell
AON Cell
Decap Cells
Decap Cells
Blockages in VLSI
What are Placement and Routing Blockages in VLSI? There are basically two types of blockages in VLSI,.i.e., Placement Blockages and Routing Blockages. The Placement Blockages are again classified into three types. They are hard blockages, soft blockages and partial blockages.…
Floorplan Module Constraints in VLSI
What are Floorplan Module Constraints in VLSI? There are basically five different type of module constraint. They are as follows: A module has the attribute None, if it is not preplaced in the core design area. A module can be…
Macro Placement Guidelines
Macro Placement Guidelines After Pin placement, we place macros in the design keeping in mind below rules: One thing I am sure that if you read the below points carefully, you will be able to easily place macros for any…
Macros in VLSI
What are Macros? Macro Cells are the Memory cells. These IPs have been designed by some other Analog design team, which can be used in the floor plan stage of the design. Type of Macros There are following three types…
Floorplan
What is Floorplan? Before hitting this particular topic of Floorplan, let’s take an example of building a house. If we are going to build a house, we first specify the area for different rooms, such as balcony, kitchen, lawn, etc.…
Standard Design Constraints (.sdc)
#Clock definition: To define clock, we need following four mandatory informations. 1. Clock source: it can be a port of the design or be a pin of a cell inside the design. (typically, that is part of a clock generation…